Search results for "Current-mode logic"
showing 7 items of 7 documents
Analysis of compressor architectures in MOS current-mode logic
2010
This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS tec…
Minimum power-delay product design of MCML gates
2008
This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.
Optimum design of two-level MCML gates
2008
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCML) gates. In particular, we describe a design methodology based on the concept of crossing-point current already introduced for the optimum design of single-level MCML gates. This methodology is suited both for automated implementation and graphic estimate of the optimum design. Moreover, it clearly shows how some important design parameters affect the optimum values of delay and power consumption. Several gates were designed in an IBM 130 nm CMOS technology. The results of SPICE simulations, reported here, demonstrate the effectiveness of the proposed design methodology.
Power-aware design of MCML logarithmic adders
2010
This paper describes the low-power design of a MOS current-mode logarithmic adder. The adder utilizes the Brent-Kung tree structure. The design strategy adopted is very simple and effective. Moreover, it can be utilized also for other types of logarithmic adders. To validate it, several adders were designed in a TSMC CMOS 130nm technology. Results of simulations indicate that the proposed methodology offers a good starting point before fine-tuning the design by SPICE simulations. Finally, the tradeoff that can be realized between performance and power consumption is discussed.
A Methodology for the Design of MOS Current-Mode Logic Circuits
2010
In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitan…
Energy-Delay Efficiency of MCML Gates
2012
In this paper, the energy-delay tradeoff that can be realized between energy and delay for MCML gates is explored using the energy-efficient curve. Two metric, namely, the energy-delay gain and the delay-energy gain are employed to quantify it. Moreover, a methodology is introduced for the minimization of the energy-delay product. Experiments were performed in 130nm and 45nm technologies.
Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current
2005
Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.